FPGA platforms provide many potential advantages over more traditional computing platforms. In a wide range of applications, computations mapped directly to FPGAs can provide higher performance and improved energy efficiency than microprocessor-based systems, digital signal processor (DSP)-based systems, and graphics processing unit (GPU)-based systems. Furthermore, in part because of their high input/output bandwidth and flexible interfaces, FPGA platforms often provide relatively higher bandwidth and lower latency connections to sensors/actuators and to memory systems. FPGA computing platforms, like traditional processor based platforms, are a complex connection of input/output devices, memory, and computing elements (in this case FPGAs, sometimes also including non-FPGA processors). Widespread use of FPGA platforms has not reached its maximum potential, however, in part due to a lack of operating environment and software/hardware interfaces to support easy development of applications. Specifically, designers of programs to be executed using an FPGA unit cannot readily establish communication between the program and external modules/devices that the program may need to access. This lack of software support often results in long and costly application development.
There are several challenges associated with developing and executing applications on FPGA hardware platforms. First, applications to be run on FPGAs need to be translated to logic circuits from a high-level language description of those applications. While this task is generally tractable for regular computational arrays and simple data-paths, many algorithms and computing tasks require complex control, which can be difficult to design and expensive (in terms of FPGA resource requirements) to implement. Second, FPGAs generally provide no native mechanisms for developers to observe the operation of their designs, as needed for design debugging, verification, and tuning. Some FPGA vendors provide logic blocks that are able to capture and display the internal state of an FPGA, but these tools are primitive and only provide low-level signaling information. Third, high-performance interfaces, such as SERES communication blocks or DRAM channels, usually require complex control for initialization and run-time calibration resulting in complex circuit designs, which the developer of the application must provide. The developer often lacks such information, however, and programming such control and communication protocols can be cumbersome and error prone.